A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store one or more bits of data. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline. One or more memory cells can be selected for writing data thereto or reading data therefrom by applying appropriate row and column addresses to row and column decoders. In conventional memory designs, row and/or column decoders include address hold latches and pre-decoder logic, wherein input addresses are applied to the address hold latches, and wherein true and complement outputs of the address hold latches drive inputs of the pre-decoder logic. The outputs of the pre-decoder logic can then be sampled by the clock signal to begin a memory array access operation. For high-performance memories, parameter such as “setup time” and “hold time” are critical timing parameters that are specified for a given design. The setup time is defined as the minimum amount of time prior to an active edge of a clock signal that an address must be stable for the address to be correctly latched. The address hold time is defined as the minimum amount of time after the active edge of the clock signal during which address must be stable. In general, depending on the design priorities, a reduction in setup time can be achieved at the expense of increased access time, or vice versa. This tradeoff occurs when the clock signal is introduced in an address path. Consequently, circuit designers will compromise on access or hold time to improve the setup time, which is undesirable.